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LPDDR4 (LPDDR4x)

Manufacturers

low power

LPDDR4X is a variant of LPDDR4, with the difference of additional power savings by reducing the I/O voltage from 1.1 V to 0.6 V.

ECC

ECC is supported on the LPDDR4 interface. Unlike traditional ECC interfaces which require dedicated memory pins and devices, ECC is supported inline. The ECC system impact is in interface bandwidth and overall memory density, as ECC data is stored alongside non-ECC data.

  • sideband - это когда отдельный чип под ECC (для LPDDR - не бывает)
  • inline - когда из разных мест читает контроллер
  • on-die - когда всё в пямяти и дополнительно для ECC место выделено

Termination

LPDDR4 memories have software configurable on-die termination for both the data group nets. The DDR subsystem also contains software configurable on-die termination for the address/control group nets. Thus, termination is not required on any DDR signals for an LPDDR4 configuration.

VREF

LPDDR4 memories generate their own VREFCA and VREFDQ internally for the address / command bus and data bus, respectively. Similarly, the DDR PHY also provides its own reference voltage for the data group nets during reads. Thus unlike DDR3 and DDR4, VREF does not need to be generated on the board, and there is no required VREF routing for an LPDDR4 configuration.

VTT

Unlike DDR3 and DDR4, there is no required termination on the PCB of the address/control bus of an LPDDR4 configuration. All termination is handled internally (on-die). Thus, VTT does not apply for LPDDR4.

Routing

TI RockChip ref design
SE impedance 40 Ohm 4mil\0.035u\0.082 prepreg Dk4.5 - ??? Ohm
DIFF impedance 80 Ohm 3.8mil\6mil\0.035u\0.082 prepreg Dk4.5 - ??? Ohm

Balanced T traces (also referred to as T-branch traces) are split traces from source to multiple end points. The target impedance of the split trace should be 2 times the non-branched impedance.

The length/delay matching process should include a mechanism for compensating for the velocity delta between these two types of PCB interconnects. A compensation factor of 1.1 has been specified for this purpose by JEDEC. All microstrip segment lengths are to be divided by 1.1 before summation into the length matching equation. The resulting compensated length is termed the 'stripline equivalent length'.

CK and ADDR_CTRL TI
CK+ to CK- skew 0.25 ps TYP
inside ADDR_CTRL skew 3 ps TYP
CK to ADDR_CTRL skew 3 ps TYP
CK\ADDR_CTRL propagation delay 250 ps MAX
DATA TI
DQS+ to DQS- skew 0.1 ps TYP
inside DQSx + BYTEx skew 0.5 ps TYP
BYTEx\DQSx propagation delay 250 ps MAX
Propagation delay of each DQS pair must be less than propagation delay DQ/DM
Propagation delay of each DQS pair must be less than propagation delay of CK pair.

Docs

Application Notes
link ext description manufacturer version date lang
8MN HDG LPDDR4 related excerpts.pdf pdf i.MX 8M Nano LPDDR4-3200 design recommendations
NXP
NXP EN
spracn9b.pdf pdf SPRACN9B Application Report
Jacinto 7 LPDDR4 Board Design and Layout Guidelines
Texas Instruments Rev. B 2021 EN
spraar7h.pdf pdf Application Report
SPRAAR7H–August 2014–Revised Ocrtober 2018
High-Speed Interface Layout Guidelines
Texas Instruments Rev. H 2018 EN
Datasheets
link ext description manufacturer version date lang
200b_z11m_non_auto_lpddr4_lpddr4x.pdf pdf MT53D512M16D1, MT53D512M32D2, MT53D1024M32D4
200b: x16/x32 LPDDR4/LPDDR4X SDRAM
1GB, 2GB, 4GB
Micron Rev. D 3/20 2017 EN
wiki/cmp/mem/lpddr4/start.1666788533.txt.gz · Последнее изменение: 2022/10/26 12:48 — Roman Abakumov