System on Module SOM-IMX8M_UQ7 is based on the NXP i.MX8M applications processor with ARM Cortex-A53 and Cortex-M4 architecture.

Board dimensions are: 70 х 40 mm.
Printed circuit of the board is made of 12 layers, some of them are ground planes, for disturbance rejection.

The i.MX 8M Quad processor feature advanced implementation of a quad Arm®Cortex®-A53 core, which operates at speeds of up to 1.5 GHz. A general purpose Cortex®-M4 core processor is for low-power processing. The DRAM controller supports 32-bit/16-bit LPDDR4, DDR4, and DDR3L memory. There are a number of other interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, displays, and camera sensors. The i.MX 8M Quad and i.MX 8M Dual processors have hardware acceleration for video playback up to 4K, and can drive the video outputs up to 60 fps.

Figure 6 shows the functional modules in the i.MX 8M Quad processor system.

SOM-IMX8M_UQ7 is available with dual rank Samsung DDR4 memory K4A4G165.

The 4Gb DDR4 SDRAM is organized as a 32Mbit x 16 I/Os x 8banks device.
This synchronous device achieves high speed double-data-rate transfer rates of up to 2666Mb/sec/pin (DDR4-2666) for general applications.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
The DDR4 device operates with a single 1.2V (1.14V~1.26V) power supply, 1.2V (1.14V~1.26V) VDDQ and 2.5V (2.375V~2.75V) VPP.

SOM-IMX8M_UQ7 has Micron NAND Flash device MT29F32 on board. Flash memory use a highly multiplexed 8-bit bus to transfer data, addresses, and instructions.
This flash device additionally includes a synchronous data interface forhigh-performance I/O operations.
When the synchronous interface is active, WE# becomes CLK and RE# becomes W/R#. Data transfers include a bidirectional data strobe(DQS).

SOM-IMX8M_UQ7 has Microchip Technology Inc. 2 Kbit I2C Serial Electrically Erasable PROM (EEPROM) 24AA025 on board.
The EEPROM has a page write capability for up to 16 bytes of data.
The device is organized as two blocks of 128 x 8-bit memory with a 2-wire serial interface.

The SOM-IMX8M_UQ7 features ROHM BD71837 as a Power Management Integrated circuit (PMIC) designed specifically for use with NXP’s i.MX8M series of application processors.
The PMIC regulates all power rails required on SOM from a single power supply with 5V.

The PMIC is fully programmable via the I2C interface and associated register map.
Software reset signal (WDOG_B) is used to perform a complete reset of the SOM-IMX8M_UQ7 module.
Reset button is installed on the motherboard for a complete reboot.

SOM-IMX8M_UQ7 has NXP Real-Time Clock (RTC) PCF8523 on board.
Data is transferred serially via the I2C-bus with a maximum data rate of 1000 kbit/s.
Alarm and timer functions are available with the possibility to generate a wake-up signal on an interrupt pin.
The PCF8523 has a backup battery switch-over circuit, which detects power failures and automatically switches to the battery supply when a power failure occurs.

SOM-IMX8M_UQ7 has Silicon Labs Ultra Low Power Wi-Fi transceiver or network co-processor (NCP) WF200С on board.

WF200 is a Wi-Fi network co-processor low energy, and low cost, with two antenna ports, Crystal Oscillator, One Time Programmable Memory, and several GPIOs for interfacing with multi-protocol and RF Front End Module controls.

SDIO interface using to communicate with the external host controller.

SOM-IMX8M_UQ7 has Microchip CAN controller MCP2515 on board.
The MCP2515 is used standard serial peripheral interface (SPI) to communicate with the i.MX8M processor.

SOM-IMX8M_UQ7 has an ARM Cortex M3 microcontroller based USB 3.0 to serial ATA bridge TUSB9261 on board.

It provides the necessary hardware and firmware to implement a USB attached SCSI protocol (UASP)-compliant mass storage device suitable for bridging hard disk drives (HDD),
solid state disk drives (SSD), optical drives, and other compatible SATA 1.5-Gbps or SATA 3.0-Gbps devices to a USB 3.0 bus.

A KDS 40 MHz crystal resonator DSX321G is used as the primary clock source.

The Winbond SPI flash device W25X10 contains firmware that loads into TUSB9261 after RESET.

SOM-IMX8M_UQ7 is available with completely integrated triple-speed (10BASE-T/100BASE-TX/1000BASE-T) Micrel Ethernet physicallayer transceiver KSZ9031 for transmission and reception of data on standard CAT-5 unshielded twisted pair (UTP) cable.
The KSZ9031 provides the Reduced Gigabit Media Independent Interface (RGMII) for direct connection to RGMII MACs in Gigabit Ethernet processors and switches for data transfer at 10/100/1000 Mbps.

SOM-IMX8M_UQ7 has Texas Instruments single channel DSI to dual-link LVDS bridge SN65DSI84 on board.
The SN65DSI84 features a single-channel MIPI D-PHY receiver front-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps.
It has a range of power management features including lowswing LVDS outputs, and the MIPI defined ultra-low power state (ULPS) support.
The SN65DSI84 is well suited for WUXGA 1920 x 1200 at 60 frames per second, with up to 24 bits-perpixel.
Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.
The bridge decodes MIPI DSI and converts the formatted video data stream to a FlatLink compatible LVDS output.
It is offering a DualLink LVDS, Single-Link LVDS interface with four data lanes per link.

SOM-IMX8M_UQ7 has one MXM2 connector (X2 slot) with 230 contacts in 0.5 mm increments for communication with the motherboard Q7_Base.
The pin assignment see in Appendix 1.

SOM-IMX8M_UQ7 has one HIROSE FPC/FFC connector FH12A-36S-0.5SH (55) for connecting camera.

SOM-IMX8M_UQ7 has one MOLEX micro-coaxial connector 73412-0114 for connecting a WIFI antenna.

Two MIPI CSI interfaces are available on SOM-IMX8M_UQ7.

MIPI CSI interface provides transfering image data directly from the camera or sensor module to the processor.
This standard also specifies an interface for a camera configuration via I²C, namely CCI (Camera Control Interface).
With MIPI CSI-2, the image data are transferred serially through individual lanes.

Four USB interfaces are available on SOM-IMX8M_UQ7:

• 1х USB 3.0 OTG (port 1);
• 2х USB 3.0 (USB 3.0 HUB) (port 2,3);
• 1x USB 2.0 (USB 3.0 HUB).

Two PCIe interfaces are available on SOM-IMX8M_UQ7.

SOM-IMX8M_UQ7 has Pericom Semiconductor 4-output low power PCIE GEN1-2-3 buffer PI6CDBL401B with integrated output terminations providing Zo=100Ω.
The device has an output control function via the I2C-bus.
Device Address: 0x1101011.

One Gigabit Ethernet interface is available on SOM-IMX8M_UQ7.

The Ethernet interface supports triple speed 10/100/1000 Mbit/s Ethernet MAC (compliant with the IEEE802.3-2002 standard) and compatibles with half- or full-duplex 10/100 Mbit/s Ethernet LANs and full-duplex gigabit Ethernet LANs.

One SDIO (SD2) interface is available on SOM-IMX8M_UQ7.

Supports SD/SDIO standard, up to version 3.0, MMC standard, up to version 5.0, 1-bit / 4-bit SD and SDIO (SD2) modes, 1-bit / 4-bit / 8-bit MMC (SD1) mode.

One UART (UART2) interface is available on SOM-IMX8M_UQ7.

The Universal Asynchronous Receiver/Transmitter (UART) provides serial communication capability with external devices through a level converter.

Two I2C interfaces are available on SOM-IMX8M_UQ7.

I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices.

One SPI interface is available on SOM-IMX8M_UQ7 (master or slave mode).

One CAN interface is available on SOM-IMX8M_UQ7.

SOM-IMX8M_UQ7 has MICROCHIP stand-alone CAN controller with SPI Interface MCP2515 on board.

The MCP2515 interfaces with processor via a standard Serial Peripheral Interface (SPI).

One HDMI interface is available on SOM-IMX8M_UQ7.

One full duplex serial audio interface with frame synchronization is available on SOM-IMX8M_UQ7.

Maximum frame size is 32 words. Word size is from 8 to 32 bits.

Two LVDS interfaces are available on SOM-IMX8M_UQ7.

The MIPIDSI→2LVDS bridge decodes MIPI DSI packets and converts the formatted video data stream to LVDS.

There are 8 pins that can be used for implementation of Low Pin Count (LPC) Bus interface or as General Purpose I/Os (GPIO).

When SOM-IMX8M_UQ7 is programmed for LPC Interface, following signals will be available:

When the Q7 module is programmed for GPIOs, all previous signals are not available and corresponding pins on Qseven connector are General Purpose I/Os, bidirectional signals at +3.3V electrical level.

Q7 connector has signals to control power buses and power states.

One UART_debug (UART1) interface is available on SOM-IMX8M_UQ7.

One I2C (I2C1) interface (for communication between processor and peripherals) is available on SOM-IMX8M_UQ7.