Board dimensions are: 70 х 40 mm.
Printed circuit of the board is made of 12 layers, some of them are ground planes, for disturbance rejection.
Module mechanical dimensions
Main Hardware Components
Component Location
Top View
Component Location. Top View
Component description on the board (Top side)
Designator
P/N
Description
U1
SN65DSI84ZQER
MIPIDSI→2LVDS bridge
U2
KSZ9031RNXI_
Ethernet PHY
U3
74AVCH2T45GT,115
Dual-bit, dual-supply voltage level translator/transceiver
U4
MIMX8MQ6CVAHZAB
Processor
U5
K4A4G165WE-BIRC
DDR4 SDRAM
U6
K4A4G165WE-BIRC
DDR4 SDRAM
U10
TUSB9261IPVP
USB3.0→SATA bridge
U11
USB5744-I/2G
USB3 HUB
U14
PI6CDBL401BZHI_
4-Output Low Power PCIE GEN1-2-3 Buffer
U28
PAM2316AGCADJ
DCDC Converter 5V→1.2V
U29
PCF8523TK/1,118
RTC
U31
BD71837AMWV_
PMIC
U32
74AVCH2T45GT,115
Dual-bit, dual-supply voltage level translator/transceiver
Bottom View
Component Location. Bottom View
Component description on the board (Bottom side)
Designator
P/N
Description
U7
MT29F32G08CBADBWP-12IT:D
NAND Flash Memory
U8
MCP2515-I/ML
CAN Controller
U9
W25X10CLUXIG
Flash Memory 1Mb
U12
WF200C
Wi-Fi Network Co-Processor
U15
PCA9540BGD,125
2-channel I2C-bus multiplexer
U16
K4A4G165WE-BIRC
DDR4 SDRAM
U17
K4A4G165WE-BIRC
DDR4 SDRAM
U18
TPS51206DSQ_
DDR Termination Regulator
U24
PAM2305CGFADJ
DCDC Converter 5V→2.5V
U27
PAM2305CGFADJ
DCDC Converter 5V→1.1V
U30
24AA025E48T-I/OT
2K I2C Serial EEPROM
Processor
The i.MX 8M Quad processor feature advanced implementation of a quad Arm®Cortex®-A53 core,
which operates at speeds of up to 1.5 GHz. A general purpose Cortex®-M4 core processor is for low-power processing.
The DRAM controller supports 32-bit/16-bit LPDDR4, DDR4, and DDR3L memory.
There are a number of other interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, displays, and camera sensors.
The i.MX 8M Quad and i.MX 8M Dual processors have hardware acceleration for video playback up to 4K, and can drive the video outputs
up to 60 fps.
Figure 6 shows the functional modules in the i.MX 8M Quad processor system.
i.MX 8M Quad function modules
Memory
SDRAM
SOM-IMX8M_UQ7 is available with dual rank Samsung DDR4 memory K4A4G165.
The 4Gb DDR4 SDRAM is organized as a 32Mbit x 16 I/Os x 8banks device.
This synchronous device achieves high speed double-data-rate transfer rates of up to 2666Mb/sec/pin (DDR4-2666) for general applications.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
The DDR4 device operates with a single 1.2V (1.14V~1.26V) power supply, 1.2V (1.14V~1.26V) VDDQ and 2.5V (2.375V~2.75V) VPP.
Flash memory
SOM-IMX8M_UQ7 has Micron NAND Flash device MT29F32 on board.
Flash memory use a highly multiplexed 8-bit bus to transfer data, addresses, and instructions.
This flash device additionally includes a synchronous data interface forhigh-performance I/O operations.
When the synchronous interface is active, WE# becomes CLK and RE# becomes W/R#. Data transfers include a bidirectional data strobe(DQS).
EEPROM
SOM-IMX8M_UQ7 has Microchip Technology Inc. 2 Kbit I2C Serial Electrically Erasable PROM (EEPROM) 24AA025 on board.
The EEPROM has a page write capability for up to 16 bytes of data.
The device is organized as two blocks of 128 x 8-bit memory with a 2-wire serial interface.
Power
Power Management Integrated circuit (PMIC)
The SOM-IMX8M_UQ7 features ROHM BD71837 as a Power Management Integrated circuit (PMIC) designed specifically for use with NXP’s i.MX8M series of application processors.
The PMIC regulates all power rails required on SOM from a single power supply with 5V.
The PMIC is fully programmable via the I2C interface and associated register map.
Software reset signal (WDOG_B) is used to perform a complete reset of the SOM-IMX8M_UQ7 module.
Reset button is installed on the motherboard for a complete reboot.
Real-Time Clock (RTC)
SOM-IMX8M_UQ7 has NXP Real-Time Clock (RTC) PCF8523 on board.
Data is transferred serially via the I2C-bus with a maximum data rate of 1000 kbit/s.
Alarm and timer functions are available with the possibility to generate a wake-up signal on an interrupt pin.
The PCF8523 has a backup battery switch-over circuit, which detects power failures and automatically switches to the battery supply when a power failure occurs.
WIFI
SOM-IMX8M_UQ7 has Silicon Labs Ultra Low Power Wi-Fi transceiver or network co-processor (NCP) WF200С on board.
WF200 is a Wi-Fi network co-processor low energy, and low cost, with two antenna ports, Crystal Oscillator, One Time Programmable Memory,
and several GPIOs for interfacing with multi-protocol and RF Front End Module controls.
SDIO interface using to communicate with the external host controller.
CAN controller
SOM-IMX8M_UQ7 has Microchip CAN controller MCP2515 on board.
The MCP2515 is used standard serial peripheral interface (SPI) to communicate with the i.MX8M processor.
USB3.0->SATA bridge
SOM-IMX8M_UQ7 has an ARM Cortex M3 microcontroller based USB 3.0 to serial ATA bridge TUSB9261 on board.
It provides the necessary hardware and firmware to implement a USB attached SCSI protocol (UASP)-compliant mass storage device suitable for bridging hard disk drives (HDD),
solid state disk drives (SSD), optical drives, and other compatible SATA 1.5-Gbps or SATA 3.0-Gbps devices to a USB 3.0 bus.
A KDS 40 MHz crystal resonator DSX321G is used as the primary clock source.
The Winbond SPI flash device W25X10 contains firmware that loads into TUSB9261 after RESET.
Gigabit Ethernet PHY
SOM-IMX8M_UQ7 is available with completely integrated triple-speed (10BASE-T/100BASE-TX/1000BASE-T) Micrel Ethernet physicallayer
transceiver KSZ9031 for transmission and reception of data on standard CAT-5 unshielded twisted pair (UTP) cable.
The KSZ9031 provides the Reduced Gigabit Media Independent Interface (RGMII) for direct connection to RGMII MACs in Gigabit Ethernet
processors and switches for data transfer at 10/100/1000 Mbps.
MIPIDSI->2LVDS bridge
SOM-IMX8M_UQ7 has Texas Instruments single channel DSI to dual-link LVDS bridge SN65DSI84 on board.
The SN65DSI84 features a single-channel MIPI D-PHY receiver front-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps.
It has a range of power management features including lowswing LVDS outputs, and the MIPI defined ultra-low power state (ULPS) support.
The SN65DSI84 is well suited for WUXGA 1920 x 1200 at 60 frames per second, with up to 24 bits-perpixel.
Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.
The bridge decodes MIPI DSI and converts the formatted video data stream to a FlatLink compatible LVDS output.
It is offering a DualLink LVDS, Single-Link LVDS interface with four data lanes per link.
External connectors
Component Location. Top View
Designator
P/N
Description
X1
FH12A-36S-0.5SH(55)
FPC / FFC camera connector
X2
MXM-II
MXM-II format connector for connecting with a motherboard
XW1
73412-0114
Microcoaxial WIFI Connector
QSeven Connector
SOM-IMX8M_UQ7 has one MXM2 connector (X2 slot) with 230 contacts in 0.5 mm increments for communication with the motherboard Q7_Base.
The pin assignment see in Appendix 1.
Camera connector
SOM-IMX8M_UQ7 has one HIROSE FPC/FFC connector FH12A-36S-0.5SH (55) for connecting camera.
WIFI antenna connector
SOM-IMX8M_UQ7 has one MOLEX micro-coaxial connector 73412-0114 for connecting a WIFI antenna.
Interfaces
WIFI
Wi-Fi
MIPI CSI2
Two MIPI CSI interfaces are available on SOM-IMX8M_UQ7.
MIPI CSI interface provides transfering image data directly from the camera or sensor module to the processor.
This standard also specifies an interface for a camera configuration via I²C, namely CCI (Camera Control Interface).
With MIPI CSI-2, the image data are transferred serially through individual lanes.
CSI2
X1 MIPI CSI interface signals
Signal Name
Pin(s)
Direction
Voltage
standard
Description
Connection
CAM_PWR
1
3V3
Power.
CAM_PWR
2
3V3
Power.
CAM0_CSI_D0+
3
out
CSI2 Camera 0 Data Lane 0.
U4.B23
CAM0_CSI_D0-
4
out
U4.A23
GND
5
Power.
CAM0_CSI_D1+
6
out
CSI2 Camera 0 Data Lane 1.
U4.D22
CAM0_CSI_D1-
7
out
U4.C22
GND
8
Power.
CAM0_CSI_D2+
9
out
CSI2 Camera 0 Data Lane 2.
U4.C23
CAM0_CSI_D2-
10
out
U4.B24
CAM0_RST#
11
in
1V8
Camera 0 Reset.
U4.P7
CAM0_CSI_D3+
12
out
CSI2 Camera 0 Data Lane 3.
U4.D21
CAM0_CSI_D3-
13
out
U4.C21
GND
14
Power.
CAM0_CSI_CLK+
15
out
CSI2 Camera 0 Differential Clock.
U4.B22
CAM0_CSI_CLK-
16
out
U4.A22
GND
17
Power.
CAM0_I2C_CLK
18
in
1V8
PU 2k2Ω
Camera 0 Control I2C Interface, CLK.
U15.5
CAM0_I2C_DAT
19
in/out
1V8
PU 2k2Ω
Camera 0 Control I2C Interface, DATA.
U15.4
CAM0_ENA#
20
in
1V8
Camera 0 Enable.
U4.T7
MCLK
21
in
Master Clock.
U4.K7
CAM1_ENA#
22
in
1V8
Camera 1 Enable.
U4.P5
CAM1_I2C_CLK
23
out
1V8
PU 2k2Ω
Camera 1 Control I2C Interface, CLK.
U15.8
CAM1_I2C_DAT
24
out
1V8
PU 2k2Ω
Camera 1 Control I2C Interface, DATA.
U15.7
GND
25
Power
CAM1_CSI_CLK+
26
out
CSI2 Camera 1 Differential Clock.
U4.B19
CAM1_CSI_CLK-
27
out
U4.A19
GND
28
Power.
CAM1_CSI_D0+
29
out
CSI2 Camera 1 Data Lane 0.
U4.D20
CAM1_CSI_D0-
30
out
U4.C20
CAM1_RST#
31
in
1V8
Camera 1 Reset.
U4.N6
CAM1_CSI_D1+
32
out
CSI2 Camera 1 Data Lane 1.
U4.B20
CAM1_CSI_D1-
33
out
U4.A20
GND
34
Power.
CAM0_GPIO
35
in/out
1V8
GPIO for Camera 0.
U4.P4
CAM1_GPIO
36
in/out
1V8
GPIO for Camera 1.
U4.N5
USB
Four USB interfaces are available on SOM-IMX8M_UQ7:
1х USB 3.0 OTG (port 1);
2х USB 3.0 (USB 3.0 HUB) (port 2,3);
1x USB 2.0 (USB 3.0 HUB).
USB block diagram
Q7 USB signals
Signal Name
Pin(s)
Direction
Voltage
standard
Description
Connection
USB_P0+
96
in/out
Universal Serial Bus Port #0 differential pair.
U11.8
USB_P0-
94
U11.9
USB_P1+
95
in/out
Universal Serial Bus Port #1 differential pair.
U4.A14
USB_P1-
93
U4.B14
USB_P2+
90
in/out
Universal Serial Bus Port #2 differential pair.
U11.1
USB_P2-
88
U11.2
USB_P3+
89
in/out
Universal Serial Bus Port #3 differential pair.
U11.17
USB_P3-
87
U11.18
USB_P4+/USB_SSRX2+
84
in/out
USB Super Speed Port #2 receive differential pair.
U4.A12
USB_P4-/USB_SSRX2-
82
U4.B12
USB_P5+/USB_SSTX2+
83
out
USB Super Speed Port #2 transmit differential pair, AC coupled 0u1F.
U4.A13
USB_P5-/USB_SSTX2-
81
U4.B13
USB_P6+/USB_SSRX0+
78
in/out
USB Super Speed Port #0 receive differential pair.
U11.13
USB_P6-/USB_SSRX0-
76
U11.14
USB_P7+/USB_SSTX0+
77
in/out
USB Super Speed Port #0 transmit differential pair, AC coupled 0u1F.
U11.10
USB_P7-/USB_SSTX0-
75
U11.11
USB_SSRX1+
132
in
USB Super Speed Port #1 receive differential pair.
U11.3
USB_SSRX1-
134
U11.4
USB_SSTX1+
144
out
USB Super Speed Port #1 transmit differential pair, AC coupled 0u1F.
U11.6
USB_SSTX1-
146
U11.7
USB_0_1_OC#
86
out
3V3
PU 10kΩ
USB Over Current Detect Input. This pin used for overcurrent detection of USB Port#0 and #1.
U4.J4
USB_2_3_OC#
85
out
3V3
PU 10kΩ
USB Over Current Detect Input. This pin has to be used for overcurrent detection of USB Ports #2 and/or #3.
U4.E1
USB_4_5_OC#
80
out
3V3
PU 10kΩ
USB Over Current Detect Input. This pin used for overcurrent detection of USB Port #4 and/or #5.
U4.H1
USB_6_7_OC#
79
in
3V3
PU 10kΩ
USB Over Current Detect Input. This pin used for overcurrent detection of USB Port #6 and/or #7.
U4.K1
USB_VBUS
91
in
3V3
USB Client mode Power Input.
U4.D14
USB_ID
92
in
3V3
PU 10kΩ
USB ID Input. USB Port #1 has set to work in Host mode.
U4.C14
USB_OTG_PEN
56
out
3V3
USB Power enable pin for USB Port 1.
U4.L1
PCIe
Two PCIe interfaces are available on SOM-IMX8M_UQ7.
PCI Express Reference Clock for channel 0 to 3, Differential Pair.
U14.22
PCIE_CLK_REF-
157
U14.23
PCIE_WAKE#
156
in
3V3
PU 10kΩ
Wake-up signal of the QSeven module system.
U4.K5
PCIE_RST#
158
out
3V3
Reset signal for devices on the motherboard.
U4.K4
PCIE GEN1-2-3 buffer
SOM-IMX8M_UQ7 has Pericom Semiconductor 4-output low power PCIE GEN1-2-3 buffer PI6CDBL401B with integrated output terminations providing Zo=100Ω.
The device has an output control function via the I2C-bus.
Device Address: 0x1101011.
SATA (USB3.0->SATA bridge)
USB3.0→SATA bridge
Q7 SATA signals
Signal Name
Pin(s)
Direction
Voltage
standard
Description
Connection
SATA0_TX+
29
out
Serial ATA Channel #0 Transmit differential pair, AC coupled 0u1F.
U10.57
SATA0_TX-
31
U10.56
SATA0_RX+
35
in
Serial ATA Channel #0 Receive differential pair, AC coupled 0u1F.
U10.60
SATA0_RX-
37
U10.59
SATA_ACT#
33
out
3V3
Serial ATA Activity Led.
U10.2
SATA1_TX+
30
out
Serial ATA channel 1, Receive Input differential pair.
Not used.
SATA1_TX-
32
SATA1_RX+
36
in
Serial ATA channel 1, Transmit Output differential pair.
Not used.
SATA1_RX-
38
Gigabit Ethernet
One Gigabit Ethernet interface is available on SOM-IMX8M_UQ7.
The Ethernet interface supports triple speed 10/100/1000 Mbit/s Ethernet MAC (compliant with the IEEE802.3-2002 standard)
and compatibles with half- or full-duplex 10/100 Mbit/s Ethernet LANs and full-duplex gigabit Ethernet LANs.
Gigabit Ethernet
Q7 Gigabit Ethernet signals
Signal Name
Pin(s)
Direction
Voltage
standard
Description
Connection
GBE_MDI0+
12
in/out
Media Dependent Interface (MDI) I/O differential pair #0.
The MDI can operate in 1000, 100, and 10Mbit/sec modes.
This signal pair is used for all modes.
U2.2
GBE_MDI0-
10
U2.3
GBE_MDI1+
11
in/out
Media Dependent Interface (MDI) I/O differential pair #1.
The MDI can operate in 1000, 100, and 10Mbit/sec modes.
This signal pair is used for all modes.
U2.5
GBE_MDI1-
9
U2.6
GBE_MDI2+
6
in/out
Media Dependent Interface (MDI) I/O differential pair #2.
The MDI can operate in 1000, 100, and 10Mbit/sec modes.
This signal pair is only used for 1000Mbit/sec Gigabit Ethernet mode.
U2.7
GBE_MDI2-
4
U2.8
GBE_MDI3+
5
in/out
Media Dependent Interface (MDI) I/O differential pair #3.
The MDI can operate in 1000, 100, and 10Mbit/sec modes.
This signal pair is only used for 1000Mbit/sec Gigabit Ethernet mode.
U2.9
GBE_MDI3-
3
U2.10
GBE_ACT#
14
out
3V3
Ethernet controller activity indicator.
U3.7
GBE_LINK#
13
out
3V3
Ethernet controller link indicator.
U3.6
GBE_LINK100#
7
out
3V3
Ethernet controller 100Mbps link indicator.
Not used.
GBE_LINK1000#
8
out
3V3
Ethernet controller 1Gbps link indicator.
U3.6
GBE_CTREF
15
out
Reference voltage for Ethernet channel 0 magnetics center tap.
Not used.
SDIO
One SDIO (SD2) interface is available on SOM-IMX8M_UQ7.
Supports SD/SDIO standard, up to version 3.0, MMC standard, up to version 5.0, 1-bit / 4-bit SD and SDIO (SD2) modes,
1-bit / 4-bit / 8-bit MMC (SD1) mode.
SDIO interface
Q7 SDIO signals
Signal Name
Pin(s)
Direction
Voltage
standard
Description
Connection
SDIO_CD#
43
in/out
3V3
PU 10kΩ
SDIO Card Detect. This signal indicates when a SDIO/MMC card is present.
U4.L21
SDIO_CLK
42
out
3V3
SDIO Clock. With each cycle of this signal a one-bit transfer on the command and each data line occurs.
U4.L22
SDIO_CMD
45
in/out
3V3
SDIO Command/Response line. This signal is used for card initialization and for command transfers.
U4.M22
SDIO_LED
44
out
3V3
SDIO LED. Used to drive an external LED to indicate when transfers occur on the bus.
Not used.
SDIO_WP
46
in/out
3V3
SDIO Write Protect. This signal denotes the state of the write-protect tab on SD cards.
U4.M21
SDIO_PWR#
47
out
3V3
SDIO Power Enable. This signal is used to enable the power being supplied to a SD/MMC card device.
U4.R22
SDIO_DAT[0÷7]
48-51
in/out
3V3
SDIO data bus. SDIO_DAT0 signal is used for all communication modes. SDIO_DAT[1 ÷ 3] signals are required for 4-bit SDIO communication modes. SDIO_DAT[4÷7] not used.
SDIO_DAT[0÷3] - [U4.N22 U4.N21 U4.P22 U4.P21]
UART
One UART (UART2) interface is available on SOM-IMX8M_UQ7.
The Universal Asynchronous Receiver/Transmitter (UART) provides serial communication capability with external devices through a level converter.
UART interface
Q7 UART signals
Signal Name
Pin(s)
Direction
Voltage
standard
Description
Connection
UART0_TX
171
out
3V3
UART Interface, Serial data Transmit line.
U4.D6
UART0_RX
177
in
3V3
PU 10kΩ
UART Interface, Serial data Receive line.
U4.B6
UART0_RTS#
172
out
3V3
UART Interface, Handshake signal, Request to Send line.
U4.D7
UART0_CTS#
178
in
3V3
UART Interface, Handshake signal, Clear to Send line.
U4.C6
I2C
Two I2C interfaces are available on SOM-IMX8M_UQ7.
I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices.
I2C interface
Q7 I2C signals
Signal Name
Pin(s)
Direction
Voltage
standard
Description
Connection
SMB_CLK
60
in/out
3V3
PU 4k7Ω
SM Bus control clock line for System Management.
U4.G8
SMB_DAT
62
in/out
3V3
PU 4k7Ω
SM Bus control data line for System Management.
U4.E9
SMB_ALERT#
64
in/out
3V3
PU 4k7Ω
SM Bus Alert line for System Management.
Not used.
GP0_I2C_CLK
66
in/out
3V3
PU 4k7Ω
General purpose I2C Bus clock line.
U4.G7
GP0_I2C_DAT
68
in/out
3V3
PU 4k7Ω
General purpose I2C Bus data line.
U4.F7
SPI
One SPI interface is available on SOM-IMX8M_UQ7 (master or slave mode).
SPI interface
Q7 SPI signals
Signal Name
Pin(s)
Direction
Voltage
standard
Description
Connection
SPI_MOSI
199
out
3V3
SPI Master Out Slave In (module QSeven → SPI devices (motherboard)).
U4.A4
SPI_MISO
201
in
3V3
SPI Master In Slave Out ( SPI devices(motherboard)→ module QSeven).
U4.B4
SPI_SCK
203
out
3V3
SPI Clock.
U4.D5
SPI_CS0#
200
out
3V3
SPI primary Chip select.
U4.D4
SPI_CS1#
202
out
3V3
SPI secondary Chip select.
Not used.
CAN
One CAN interface is available on SOM-IMX8M_UQ7.
SOM-IMX8M_UQ7 has MICROCHIP stand-alone CAN controller with SPI Interface MCP2515 on board.
The MCP2515 interfaces with processor via a standard Serial Peripheral Interface (SPI).
CAN interface
Q7 CAN signals
Signal Name
Pin(s)
Direction
Voltage
standard
Description
Connection
CAN0_TX
129
out
3V3
CAN Transmit for CAN Bus Channel 0.
U8.19
CAN0_RX
130
in
3V3
CAN Receive for CAN Bus Channel 0.
U8.20
HDMI
One HDMI interface is available on SOM-IMX8M_UQ7.
HDMI interface
Q7 HDMI/DP signals
Signal Name
Pin(s)
Direction
Voltage
standard
Description
Connection
DP_LANE3+
131
out
Display Port differential pair #3, AC coupled 0u1F.
U4.M1
DP_LANE3-
133
out
U4.M2
DP_LANE2+
143
out
Display Port differential pair #2, AC coupled 0u1F.
U4.N2
DP_LANE2-
145
out
U4.N1
DP_LANE1+
137
out
Display Port differential pair #1.
U4.U2
DP_LANE1-
139
out
U4.U1
DP_LANE0+
149
out
Display Port differential pair #0.
U4.T1
DP_LANE0-
151
out
U4.T2
HDMI_CTRL_DAT
150
in/out
3V3
PU 10kΩ
DDC Data line for HDMI panel.
U4.P3
HDMI_CTRL_CLK
152
in/out
3V3
PU 10kΩ
DDC Clock line for HDMI panel.
U4.R3
HDMI_HPD#
153
in
3V3
Hot Plug Detect Output signal.
U4.W2
HDMI_CEC
124
in/out
3V3
HDMI Consumer Electronics Control (CEC) Line.
U4.W3
DP_AUX+
138
in/out
Display Port auxiliary channel differential pair.
U4.V1
DP_AUX+
140
in/out
U4.V2
DP_HPD#
154
in
DisplayPort Hot Plug Detect output signal.
Not used.
Audio interface AC97 (SAI)
One full duplex serial audio interface with frame synchronization is available on SOM-IMX8M_UQ7.
Maximum frame size is 32 words. Word size is from 8 to 32 bits.
Audio interface
Q7 Audio signals
Signal Name
Pin(s)
Direction
Voltage
standard
Description
Connection
HDA_SYNC
59
out
3V3
Serial Bus Synchronization.
U4.H4
HDA_RST#
61
out
3V3
HD Audio Codec Reset.
U4.H5
HDA_BCLK
63
out
3V3
HD Audio Serial Bit Clock from Codec.
U4.J5
HDA_SDO
67
out
3V3
HD Audio Serial Data Output to Codec.
U4.G5
HDA_SDI
65
in
3V3
HD Audio Serial Data Input from Codec.
U4.H6
LVDS (MIPI DSI -> LVDS)
Two LVDS interfaces are available on SOM-IMX8M_UQ7.
The MIPIDSI→2LVDS bridge decodes MIPI DSI packets and converts the formatted video data stream to LVDS.
LVDS interface
Q7 LVDS signals
Signal Name
Pin(s)
Direction
Voltage
standard
Description
Connection
LVDS_A0+
99
out
LVDS Channel #0 differential data pair #0.
U1.C8
LVDS_A0-
101
U1.C9
LVDS_A1+
103
out
LVDS Channel #0 differential data pair #1.
U1.D8
LVDS_A1-
105
U1.D9
LVDS_A2+
107
out
LVDS Channel #0 differential data pair #2.
U1.E8
LVDS_A2-
109
U1.E9
LVDS_A3+
113
out
LVDS Channel #0 differential data pair #3.
U1.G8
LVDS_A3-
115
U1.G9
LVDS_A_CLK+
119
out
LVDS Channel #0 differential Clock.
U1.F8
LVDS_A_CLK-
121
U1.F9
LVDS_B0+
100
out
LVDS Channel #1 differential data pair #0.
U1.B3
LVDS_B0-
102
U1.A3
LVDS_B1+
104
out
LVDS Channel #1 differential data pair #1.
U1.B4
LVDS_B1-
106
U1.A4
LVDS_B2+
108
out
LVDS Channel #1 differential data pair #2.
U1.B5
LVDS_B2-
110
U1.A5
LVDS_B3+
114
out
LVDS Channel #1 differential data pair #3.
U1.B7
LVDS_B3-
116
U1.A7
LVDS_B_CLK+
120
out
LVDS Channel #1 differential Clock.
U1.B6
LVDS_B_CLK-
122
U1.A6
LVDS_PPEN
111
out
3V3
Panel Power Enable signal. It can be used to turn On/Off the connected LVDS display.
U4.N4
LVDS_BLEN
112
out
3V3
Panel Backlight Enable signal. It can be used to turn On/Off the backlight’s lamps of connected LVDS display.
U4.M5
LVDS_BLT_CTRL/
GP_PWM_OUT0
123
out
3V3
This signal can be used to adjust the panel backlight brightness in displays supporting Pulse Width Modulated (PWM) regulations.
When backlight brightness control via PWM is not required, this signal can be used as a General Purpose PWM output.
U4.G6
LVDS_BLC_DAT
126
in/out
3V3
PU 10kΩ
I2C control data line for external Spread Spectrum Control Clock chip.
U4.M4
LVDS_BLC_CLK
128
in/out
3V3
PU 10kΩ
I2C control clock line for external Spread Spectrum Control Clock chip.
If the primary functionality is not used, it can be used as a General Purpose I²C bus #2 clock line.
U4.L5
LVDS_DID_DAT
125
in/out
3V3
PU 10kΩ
DisplayID DDC Data line for LVDS flat Panel detection.
If the primary functionality is not used, it can be used as a General Purpose I²C bus #2 data line.
U4.F8
LVDS_DID_CLK
127
in/out
3V3
PU 10kΩ
DisplayID DDC Clock line for LVDS flat Panel detection.
U4.F9
LPC и GPIO
There are 8 pins that can be used for implementation of Low Pin Count (LPC) Bus interface or as General Purpose I/Os (GPIO).
When SOM-IMX8M_UQ7 is programmed for LPC Interface, following signals will be available:
Q7 LPC/GPIO signals
Signal Name
Pin(s)
Direction
Voltage
standard
Description 1
Description 2
Connection
LPC_AD[0÷3]
185-188
in/out
3V3
LPC data bus, bidirectional signal.
In/out signals GPIO0-GPIO3
[U4.G3 U4.G4 U4.F4 U4.C3]
LPC_CLK
189
out
3V3
LPC Clock Input line.
In/out signal GPIO4
U4.F3
LPC_FRAME#
190
out
3V3
LPC Frame indicator.
This signal is used to signal the start of a new cycle of transmission, or the termination of existing cycles due to abort or time-out condition.
In/out signal GPIO5.
U4.A3
LPC_LDRQ#
192
in
3V3
LPC DMA request.
This signal is used only by peripherals requiring DMA or bus mastering.
In/out signal GPIO7.
U4.C4
SERIRQ
191
in/out
3V3
LPC Serialised IRQ request, bidirectional line.
This signal is used only by peripherals requiring Interrupt support.
In/out signal GPIO6.
U4.D3
When the Q7 module is programmed for GPIOs, all previous signals are not available and corresponding pins on Qseven connector are General Purpose I/Os, bidirectional signals at +3.3V electrical level.
Miscellaneous Signals
Power Management signals
Q7 connector has signals to control power buses and power states.
Q7 power signals
Signal Name
Pin(s)
Direction
Voltage
standard
Description
Connection
PWGIN
26
in
5
Power Good. This signal signals that power supply section is ready and stable.
U31.32
PWRBTN#
20
in
3V3
PU 10kΩ
Power Button.
U4.W21
RSTBTN#
28
in
3V3
Reset Button.
U31.37
BATLOW#
27
in
3V3
Battery Low.
Not used.
WAKE#
17
in
3V3
Wake Output.
Not used.
SUS_STAT#
19
out
3V3
Suspend status.
Not used.
SUS_S3#
18
out
3V3
PU 10kΩ
S3 status input.
SUS_S5#
16
out
3V3
PU 10kΩ
S5 State input: This signal indicates S4 or S5 (Soft Off) state.
SLP_BTN#
21
in
3V3
Sleep button.
Not used.
LID_BTN#
22
in
3V3
LID button.
Not used.
Fan Control Implementation
Q7 fan control
Signal Name
Pin(s)
Direction
Voltage
standard
Description
Connection
FAN_T_IN
195
in
3V3
Fan tachometer input (can be used as General Purpose Timer Input).
Not used.
FAN_OUT
196
out
3V3
Fan speed control (can be used as General Purpose PWM Output).
U4.F6
Thermal Management Signals
Q7 thermal management signals
Signal Name
Pin(s)
Direction
Voltage
standard
Description
Connection
THRM#
69
in
3V3
Thermal Alarm Input indicates an over temperature situation (can be used to initiate thermal throttling).
Not used.
THRMTRIP#
71
out
3V3
PU 10kΩ
Thermal Trip indicates an overheating condition of the processor.
Other signals
Q7 miscellaneous signals
Signal Name
Pin(s)
Direction
Voltage
standard
Description
Connection
WDTRIG#
70
in
3V3
PU 10kΩ
Watchdog Trigger Signal.
U4.A6
WDOUT
72
out
3V3
PU 10kΩ
Watchdog event indicator.
U4.B7
SPKR
194
out
3V3
Speaker output.
U4.E6
BIOS_DIS#
41
in
3V3
PU 10kΩ
Module BIOS disable input signal.
U4.V4
Manufacturing signals
Q7 manufacturing signals
Signal Name
Pin(s)
Direction
Voltage
standard
Description
Connection
MFG_NC0
207
in
3V3
JTAG_TCK / vendor specific control signal.
Not used.
MFG_NC3
210
in
3V3
JTAG_TMS / BOOT
Not used.
MFG_NC4
204
in
3V3
JTAG-TRST / control signal for a multiplexer circuit
+3V Real Time Clock (RTC) supply voltage. (3V backup cell input.
Used for RTC operation and storage register non-volatility in the absence of system power).
NC and reserved signals
Q7 NC and reserved signals
Signal Name
Pin(s)
Direction
Voltage
standard
Description
Comments
reserved (SDIO_LED)
44
SDIO LED. Used to drive an external LED to indicate when transfers occur on the bus.
reserved (SDIO_DAT5)
52
SDIO_DAT[4…7]
reserved (SDIO_DAT4)
53
reserved (SDIO_DAT7)
54
reserved (SDIO_DAT6)
55
NC (VCC)
211-218
These pins reserved for use in later Qseven® revisions to avoid backward compatibility issues in the future.
Debugging/development interfaces
UART debugging
One UART_debug (UART1) interface is available on SOM-IMX8M_UQ7.
UART_debug interface
Q7 UART_debug signals
Signal Name
Pin(s)
Direction
Voltage
standard
Description
Connection
MFG_NC1
209
out
3V3
Serial data line UART_TX for debugging.
U4.A7
MFG_NC2
208
in
3V3
PU 10kΩ
Serial data line UART_RX for debugging.
U4.C7
I2C
One I2C (I2C1) interface (for communication between processor and peripherals) is available on SOM-IMX8M_UQ7.
