Показаны различия между двумя версиями страницы.
| Предыдущая версия справа и слеваПредыдущая версия | |||
| wiki:if:pcie:start [2023/10/09 11:13] – Roman Abakumov | wiki:if:pcie:start [2023/10/11 20:19] (текущий) – Roman Abakumov | ||
|---|---|---|---|
| Строка 7: | Строка 7: | ||
| sort : ^pageid | sort : ^pageid | ||
| ---- | ---- | ||
| + | ===== Docs ===== | ||
| + | | https:// | ||
| + | | https:// | ||
| + | | https:// | ||
| + | | https:// | ||
| + | | https:// | ||
| + | | https:// | ||
| + | |||
| ===== Connectors ===== | ===== Connectors ===== | ||
| + | |||
| + | |||
| + | ===== Xilinx ===== | ||
| + | ==== Artix Ultrascale+ ===== | ||
| + | PCIe корка стартует нормально только если прошивка быстро загружается из флешки. | ||
| + | |||
| + | Вариант конфигурации через JTAG, а потом ребут компа или пауза в u-boot и потом загрузка Linux не прокатывают. | ||
| + | |||
| + | Возможно, | ||
| + | |||
| + | |||
| ===== SMARC ===== | ===== SMARC ===== | ||
| {{drawio> | {{drawio> | ||
| Строка 17: | Строка 36: | ||
| {{: | {{: | ||
| + | |||
| + | < | ||
| + | #define LTSSM_DETECT | ||
| + | #define LTSSM_POLLING | ||
| + | #define LTSSM_CONFIG | ||
| + | #define LTSSM_RECOVERY | ||
| + | #define LTSSM_DISABLED | ||
| + | #define LTSSM_HOTRESET | ||
| + | #define LTSSM_LOOPBACK | ||
| + | #define LTSSM_L0 | ||
| + | #define LTSSM_L0s | ||
| + | #define LTSSM_L1 | ||
| + | #define LTSSM_L2 | ||
| + | </ | ||
| + | |||
| + | < | ||
| + | detect.quiet", | ||
| + | detect.active", | ||
| + | polling.active", | ||
| + | polling.compliance", | ||
| + | polling.configuration", | ||
| + | config.linkwidthstart", | ||
| + | config.linkwidthaccept", | ||
| + | config.lanenumwait", | ||
| + | config.lanenumaccept", | ||
| + | config.complete", | ||
| + | config.idle", | ||
| + | recovery.receiverlock", | ||
| + | recovery.equalization", | ||
| + | recovery.speed", | ||
| + | recovery.receiverconfig", | ||
| + | recovery.idle", | ||
| + | L0", | ||
| + | L0s", | ||
| + | L1.entry", | ||
| + | L1.idle", | ||
| + | L2.idle", | ||
| + | L2.transmitwake", | ||
| + | disable", | ||
| + | loopback.entry", | ||
| + | loopback.active", | ||
| + | loopback.exit", | ||
| + | hotreset", | ||
| + | </ | ||
| + | |||
| + | Xilinx Xore: | ||
| + | < | ||
| + | 00: Detect.Quiet | ||
| + | 01: Detect.Active | ||
| + | 02: Polling.Active | ||
| + | 03: Polling.Compliance | ||
| + | 04: Polling.Configuration | ||
| + | 05: Configuration.Linkwidth.Start | ||
| + | 06: Configuration.Linkwidth.Accept | ||
| + | 07: Configuration.Lanenum.Accept | ||
| + | 08: Configuration.Lanenum.Wait | ||
| + | 09: Configuration.Complete | ||
| + | 0A: Configuration.Idle | ||
| + | 0B: Recovery.RcvrLock | ||
| + | 0C: Recovery.Speed | ||
| + | 0D: Recovery.RcvrCfg | ||
| + | 0E: Recovery.Idle | ||
| + | 10: L0 | ||
| + | 11-16: Reserved | ||
| + | 17: L1.Entry | ||
| + | 18: L1.Idle | ||
| + | 19-1A: Reserved | ||
| + | 20: Disabled | ||
| + | 21: Loopback_Entry_Master | ||
| + | 22: Loopback_Active_Master | ||
| + | 23: Loopback_Exit_Master | ||
| + | 24: Loopback_Entry_Slave | ||
| + | 25: Loopback_Active_Slave | ||
| + | 26: Loopback_Exit_Slave | ||
| + | 27: Hot_Reset | ||
| + | 28: Recovery_Equalization_Phase0 | ||
| + | 29: Recovery_Equalization_Phase1 | ||
| + | 2a: Recovery_Equalization_Phase2 | ||
| + | 2b: Recovery_Equalization_Phase3 | ||
| + | </ | ||