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--- wiki:if:eth:start [2022/07/18 21:06] – удалено - внешнее изменение (Unknown date) 127.0.0.1
+++ wiki:if:eth:start [2025/10/17 15:28] (текущий) – Roman Abakumov
@@ Строка 1: / Строка 1: @@
+===== Ethernet =====
+| http://iommu.com/datasheets/ | Доки |
+{{:wiki:if:eth:osi-802.3.png?640&direct}}
+===== Medium Dependent Interfaces (MDI) =====
+To communicate in a compatible manner, all stations shall
+adhere rigidly to the exact specification of physical media signals defined in the appropriate clauses
+in this standard, and to the procedures that define correct behavior of a station. The medium-independent
+aspects of the LLC sublayer and the MAC sublayer should not be taken as detracting from
+this point; communication in an Ethernet Local Area Network requires complete compatibility at the
+Physical Medium interface (that is, the physical cable interface).
+===== Attachment Unit Interface (AUI) =====
+Some DTEs are located some distance from their connection to the
+physical cable. A small amount of circuitry will exist in the Medium Attachment Unit (MAU)
+directly adjacent to the physical cable, while the majority of the hardware and all of the software will
+be placed within the DTE. The AUI is defined as a second compatibility interface. While conformance with
+this interface is not strictly necessary to ensure communication, it is recommended,
+since it allows maximum flexibility in intermixing MAUs and DTEs. The AUI may be optional or
+not specified for some implementations of this standard that are expected to be connected directly to
+the medium and so do not use a separate MAU or its interconnecting AUI cable. The PLS and PMA
+are then part of a single unit, and no explicit AUI implementation is required.
+===== Media Independent Interface (MII) =====
+It is anticipated that some DTEs will be connected to a remote
+PHY, and/or to different medium dependent PHYs. The MII is defined as a third compatibility interface.
+While conformance with implementation of this interface is not strictly necessary to ensure
+communication, it is recommended, since it allows maximum flexibility in intermixing PHYs and
+DTEs. The MII is optional.
+===== MAC<>PHY ====
+==== MII ====
+==== RMII ====
+==== Gigabit Media Independent Interface (GMII) ====
+The GMII is designed to connect a 1 Gb/s capable
+MAC or repeater unit to a 1 Gb/s PHY. While conformance with implementation of this interface is
+not strictly necessary to ensure communication, it is recommended, since it allows maximum flexibility
+in intermixing PHYs and DTEs at 1 Gb/s speeds. The GMII is intended for use as a chip-tochip interface.
+No mechanical connector is specified for use with the GMII. The GMII is optional.
+==== RGMII ====
+==== SGMII ====
+==== 10 Gigabit Attachment Unit Interface (XAUI) ====
+The XAUI is designed to extend the connection
+between a 10 Gb/s capable MAC and a 10 Gb/s PHY. While conformance with implementation of
+this interface is not necessary to ensure communication, it is recommended, since it allows maximum
+flexibility in intermixing PHYs and DTEs at 10 Gb/s speeds. The XAUI is intended for use as
+a chip-to-chip interface. No mechanical connector is specified for use with the XAUI. The XAUI is
+optional.
+==== 10 Gigabit Media Independent Interface (XGMII) ====
+The XGMII is designed to connect a 10 Gb/s
+capable MAC to a 10 Gb/s PHY. While conformance with implementation of this interface is not
+necessary to ensure communication, it allows maximum flexibility in intermixing PHYs and DTEs
+at 10 Gb/s speeds. The XGMII is intended for use as a chip-to-chip interface. No mechanical
+connector is specified for use with the XGMII. The XGMII is optional.
+==== 40 Gigabit Media Independent Interface (XLGMII) ====
+The XLGMII is designed to connect a 40 Gb/s
+capable MAC to a 40 Gb/s PHY. While conformance with implementation of this interface is not
+necessary to ensure communication, it allows flexibility in intermixing PHYs and DTEs at 40 Gb/s
+speeds. The XLGMII is a logical interconnection intended for use as an intra-chip interface. No
+mechanical connector is specified for use with the XLGMII. The XLGMII is optional.
+==== 100 Gigabit Media Independent Interface (CGMII) ====
+The CGMII is designed to connect a 100 Gb/s
+capable MAC to a 100 Gb/s PHY. While conformance with implementation of this interface is not
+necessary to ensure communication, it allows flexibility in intermixing PHYs and DTEs at 100 Gb/s
+speeds. The CGMII is a logical interconnection intended for use as an intra-chip interface. No
+mechanical connector is specified for use with the CGMII. The CGMII is optional.
+===== PMA Interface =====
+==== 40 Gigabit Attachment Unit Interface (XLAUI) ====
+The XLAUI is a physical instantiation of the PMA
+service interface to extend the connection between 40 Gb/s capable PMAs. While conformance with
+implementation of this interface is not necessary to ensure communication, it is recommended, since
+it allows maximum flexibility in intermixing PHYs and DTEs at 40 Gb/s speeds. The XLAUI is
+intended for use as a chip-to-chip or a chip-to-module interface. No mechanical connector is
+specified for use with the XLAUI. The XLAUI is optional.
+==== 100 Gigabit Attachment Unit Interface (CAUI) ====
+The CAUI is a physical instantiation of the PMA
+service interface to extend the connection between 100 Gb/s capable PMAs. While conformance
+with implementation of this interface is not necessary to ensure communication, it is recommended,
+since it allows maximum flexibility in intermixing PHYs and DTEs at 100 Gb/s speeds. The CAUI
+is intended for use as a chip-to-chip or a chip-to-module interface. No mechanical connector is
+specified for use with the CAUI. The CAUI is optional.
+==== Ten-bit Interface (TBI) ===
+The TBI is provided by the 1000BASE-X PMA sublayer as a physical
+instantiation of the PMA service interface. The TBI is recommended for 1000BASE-X systems,
+since it provides a convenient partition between the high-frequency circuitry associated with the
+PMA sublayer and the logic functions associated with the PCS and MAC sublayers. The TBI is
+intended for use as a chip-to-chip interface. No mechanical connector is specified for use with the
+TBI. The TBI is optional.
+==== RTBI ====
+==== 10 Gigabit Sixteen-Bit Interface (XSBI) ====
+The XSBI is provided as a physical instantiation of the
+PMA service interface for 10GBASE-R and 10GBASE-W PHYs. While conformance with implementation of
+this interface is not necessary to ensure communication, it provides a convenient partition between
+the high-frequency circuitry associated with the PMA sublayer and the logic functions
+associated with the PCS and MAC sublayers. No mechanical connector is specified for use with the
+XSBI. The XSBI is optional.
+===== PMD Interface =====
+==== 40 Gigabit Parallel Physical Interface (XLPPI) ====
+The XLPPI is provided as a physical instantiation
+of the PMD service interface for 40GBASE-SR4 and 40GBASE-LR4 PMDs. The XLPPI has four
+lanes. While conformance with implementation of this interface is not necessary to ensure
+communication, it allows flexibility in connecting the 40GBASE-SR4 or 40GBASE-LR4 PMDs.
+The XLPPI is intended for use as a chip-to-module interface. No mechanical connector is specified
+for use with the XLPPI. The XLPPI is optional.
+==== 100 Gigabit Parallel Physical Interface (CPPI) ====
+The CPPI is provided as a physical instantiation of
+the PMD service interface for 100GBASE-SR10 PMDs. The CPPI has ten lanes. While
+conformance with implementation of this interface is not necessary to ensure communication, it
+allows flexibility in connecting the 100GBASE-SR10 PMDs. The CPPI is intended for use as a
+chip-to-module interface. No mechanical connector is specified for use with the CPPI. The CPPI is
+optional.
+{{indexmenu>.#2|skipfile+/index|start/ nsort tsort}}

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