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wiki:cmp:mem:lpddr4:start [2023/11/27 14:47] – [Table] Roman Abakumovwiki:cmp:mem:lpddr4:start [2025/09/26 10:43] (текущий) – Roman Abakumov
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-===== LPDDR4(4x) =====+====== LPDDR4(4x) ======
  
-==== Manufacturers ====+===== Manufacturers =====
 | https://semiconductor.samsung.com/dram/lpddr/lpddr4x/ | Samsung | BGA200 up to 32Gb and more | | https://semiconductor.samsung.com/dram/lpddr/lpddr4x/ | Samsung | BGA200 up to 32Gb and more |
 | https://product.skhynix.com/products/dram/lpddr/lpddr4x_4.go | SKHynix | BGA200 up to 32Gb and more | | https://product.skhynix.com/products/dram/lpddr/lpddr4x_4.go | SKHynix | BGA200 up to 32Gb and more |
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 ==== Table ==== ==== Table ====
 | MT53D512M32D2DS-053WT:D | Micron   | LPDDR4\4x |      | 32b | 16gb | -20...85 | EOL | D9WHZ |  | MT53D512M32D2DS-053WT:D | Micron   | LPDDR4\4x |      | 32b | 16gb | -20...85 | EOL | D9WHZ | 
-| H2AB32G32D6CPAAI        | HWA LING | LPDDR4    | 3733 | 32b | 32gb | -40...95 |     |       | +| H2AB32G32D6CPAAI        | HWA LING (axeme) | LPDDR4    | 3733 | 32b | 32gb | -40...95 |     |       | 
-| W66BQ6NB / W66CQ2NQ     | Winbond  | LPDDR4X   |     |     | 2Gb / 4Gb |    |    |     | +| W66BQ6NB                | Winbond  | LPDDR4X   |     |     | 2Gb |    |    |     | 
-| NCLD4C1MA256M32\\ NCLD4C2MA512M32\\ NCLD4C2MA768M32\\ NCLD4C2MA001G32 | FORESEE | LPDDR4 |   |  |   |   |  |  |+| W66CQ2NQ                | Winbond  | LPDDR4X   |     |     | 4Gb |    |    |     | 
 +| NCLD4C1MA256M32         | FORESEE | LPDDR4 |   |  | 8Gb |   |  |  | 
 +| NCLD4C2MA512M32         | FORESEE | LPDDR4 |   |  | 16Gb |   |  |  | 
 +| NCLD4C2MA768M32         | FORESEE | LPDDR4 |   |  | 24Gb |   |  |  | 
 +| NCLD4C2MA001G32         | FORESEE | LPDDR4 |   |  | 32Gb |   |  |  |
  
  
 +===== Configurations =====
 +^ Capacity ^ Width ^ CS (Rank) ^ Channels ^ Dies ^ Link ^ Diagram ^
 +|  16 Gb | x16     | 1 CS | 1 Channel | 1 Die  | [[https://doc.inmys.ru/hash/70384c662976e351602c19c34d488449/MT53E1G32D2FW-046.pdf|MT53E1G16D1]] | {{:wiki:cmp:mem:lpddr4:x16_1cs_1ch_1die.png?240&direct}} |
 +|  16 Gb | x16+x16 | 1 CS | 2 Channel | 1 Die  | [[https://doc.inmys.ru/hash/53cb022811f61c15b55f71992e0fa862/LPDDR4_16GBIT_512MX32_200PIN_FBGA_IND.pdf|A8XAGH50ABA]] | {{:wiki:cmp:mem:lpddr4:16gb_x32_1cs.png?240&direct}} |
 +|   8 Gb | x16+x16 | 1 CS | 2 Channel | 1 Die  | [[https://doc.inmys.ru/hash/05d9a08beeed9e5d8edd20eca9200ef1/H9HCNNN8KUMLHR-NMI.pdf|H9HCNNN8KUMLHR]] | {{:wiki:cmp:mem:lpddr4:8gb_x16_1cs_2channel_1die.png?240&direct}} |
 +|  16 Gb | x16+x16 | 1 CS | 2 Channel | 1 Die  | [[https://doc.inmys.ru/hash/8f2714c2463e1c9f85671d8c3e4bbf9b/K4F6E3S4HM-MGCJ000.pdf|K4F6E3S4HM]] |{{:wiki:cmp:mem:lpddr4:16gb_x32_1cs_2ch_1die.png?240&direct}} |
 +|  16 Gb | x16+x16 | 1 CS | 2 Channel | 1 Die  | [[https://doc.inmys.ru/hash/632a5f6dbcfe6714cc1b9cd33b032c0f/RS512M32LO4D1BDS%26RS1G32LO4D2BDS-46IT_V1.3%282%29.pdf|RS512M32LO4D1BDS-46IT]] | {{:wiki:cmp:mem:lpddr4:x32_1cs_2ch_1die_rs.png?240&direct}} |
 +|  16 Gb | x16+x16 | 1 CS | 2 Channel | 2 Die  | [[https://doc.inmys.ru/hash/7d69a56cb4e9108289bb04ace3b84b89/MT53D512M32D2DS-053WTD.pdf|MT53D512M32D2]] | {{:wiki:cmp:mem:lpddr4:x32_1cs_2ch_2die.png?240&direct}} |
 +|  32 Gb | x16+x16 | 1 CS | 2 Channel | 2 Die  | [[https://doc.inmys.ru/hash/70384c662976e351602c19c34d488449/MT53E1G32D2FW-046.pdf|MT53E1G32D2]] | {{:wiki:cmp:mem:lpddr4:x32_1cs_2ch_2die.png?240&direct}} |
 +|  32 Gb | x16+x16 | 1 CS | 2 Channel | 2 Die  | [[https://doc.inmys.ru/hash/16208efa6a331401d0cffd7f6f3d2730/RS2G32LV4D4BDT-46IT.pdf|RS1G32LV4D2BDS-53BT]] | {{:wiki:cmp:mem:lpddr4:x32_1cs_2ch_2die_rs.png?240&direct}} |
 +|  16 Gb | x16+x16 | 2 CS | 2 Channel | 2 Die  | [[https://doc.inmys.ru/hash/2034638f86b84b22453ca82477f91c1a/H2AB16G32D6CIAASL.pdf|H2AB16G32D6C]] | {{:wiki:cmp:mem:lpddr4:x32_2cs_2ch_2die.png?240&direct}} |
 +|  32 Gb | x16+x16 | 2 CS | 2 Channel | 2 Die  | [[https://doc.inmys.ru/hash/632a5f6dbcfe6714cc1b9cd33b032c0f/RS512M32LO4D1BDS%26RS1G32LO4D2BDS-46IT_V1.3%282%29.pdf|RS1G32LO4D2BDS-46IT]] | {{:wiki:cmp:mem:lpddr4:x32_2cs_2ch_2die_rs1.png?240&direct}} |
 +|  32 Gb | x16+x16 | 2 CS | 2 Channel | 4 Die  | [[https://doc.inmys.ru/hash/7d69a56cb4e9108289bb04ace3b84b89/MT53D512M32D2DS-053WTD.pdf|MT53D1024M32D4]] | {{:wiki:cmp:mem:lpddr4:x32_2cs_2ch_4die.png?240&direct}} |
 +|  64 Gb | X16+x16 | 2 CS | 2 Channel | 4 Die  | [[https://doc.inmys.ru/hash/70384c662976e351602c19c34d488449/MT53E1G32D2FW-046.pdf|MT53E2G32D4]] | {{:wiki:cmp:mem:lpddr4:x32_2cs_2ch_4die.png?240&direct}} |
 +|  64 Gb | x16+x16 | 2 CS | 2 Channel | 4 Die  | [[https://doc.inmys.ru/hash/16208efa6a331401d0cffd7f6f3d2730/RS2G32LV4D4BDT-46IT.pdf|RS2G32LV4D4BDT-53BT]] | {{:wiki:cmp:mem:lpddr4:x32_2ch_2ch_4die_rs.png?240&direct}} |
 +|  64 Gb | x16+x16 | 2 CS | 2 Channel | 4 Die  | [[https://doc.inmys.ru/hash/88b89be1f383bf0e6504387401e0d5fe/RS2G32LV4D4BDT-46IT_Correct.pdf|RS2G32LV4D4BDT-46IT]] | {{:wiki:cmp:mem:lpddr4:x32_2cs_2ch_4die_rs.png?240&direct}} |
 +| 128 Gb | x16+x16 | 2 CS | 2 Channel | 8 Die  | [[https://doc.inmys.ru/hash/4eca1e431ce93a78e333dc43e876fa7c/RS4G32LV4D8BDT-53BT.pdf|RS4G32LV4D8BDT-53BT]] | {{:wiki:cmp:mem:lpddr4:x32_2cs_2ch_8die.png?240&direct}} |
  
  
-==== SKHynix ====+ 
 +===== SKHynix =====
 {{tablelayout?rowsHeaderSource=Auto&colwidth=","&tableSort=1&tableSearch=1}} {{tablelayout?rowsHeaderSource=Auto&colwidth=","&tableSort=1&tableSearch=1}}
 | H9HCNNNCPUMLXR-NEE  | PC          | LPDDR4   | 4GB    | 1.8V / 1.1V / 1.1V  | 4266Mbps  | 200Ball  | MP  | -25 |  | H9HCNNNCPUMLXR-NEE  | PC          | LPDDR4   | 4GB    | 1.8V / 1.1V / 1.1V  | 4266Mbps  | 200Ball  | MP  | -25 | 
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-==== low power ====+===== low power =====
 LPDDR4X is a variant of LPDDR4, with the difference of additional power savings by reducing the I/O voltage from 1.1 V to 0.6 V. LPDDR4X is a variant of LPDDR4, with the difference of additional power savings by reducing the I/O voltage from 1.1 V to 0.6 V.
  
  
-==== ECC ====+===== ECC =====
 ECC is supported on the LPDDR4 interface. Unlike traditional ECC interfaces which require dedicated memory ECC is supported on the LPDDR4 interface. Unlike traditional ECC interfaces which require dedicated memory
 pins and devices, ECC is supported inline. The ECC system impact is in interface bandwidth and overall memory pins and devices, ECC is supported inline. The ECC system impact is in interface bandwidth and overall memory
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   * есть p\n с ECC (https://www.issi.com/WW/pdf/43-46LQ16256-32128EA-AL.pdf), есть - без ECC (https://www.issi.com/WW/pdf/43-46LQ32256A-AL.pdf)   * есть p\n с ECC (https://www.issi.com/WW/pdf/43-46LQ16256-32128EA-AL.pdf), есть - без ECC (https://www.issi.com/WW/pdf/43-46LQ32256A-AL.pdf)
  
-==== Termination ====+===== Termination =====
 LPDDR4 memories have software configurable on-die termination for both the data group nets. The DDR LPDDR4 memories have software configurable on-die termination for both the data group nets. The DDR
 subsystem also contains software configurable on-die termination for the address/control group nets. Thus, subsystem also contains software configurable on-die termination for the address/control group nets. Thus,
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-==== VREF ====+===== VREF =====
 LPDDR4 memories generate their own VREFCA and VREFDQ internally for the address / command bus and data bus,  LPDDR4 memories generate their own VREFCA and VREFDQ internally for the address / command bus and data bus, 
 respectively. Similarly, the DDR PHY also provides its own reference voltage for the data group nets respectively. Similarly, the DDR PHY also provides its own reference voltage for the data group nets
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-==== VTT ====+===== VTT =====
 Unlike DDR3 and DDR4, there is no required termination on the PCB of the address/control bus of an LPDDR4 Unlike DDR3 and DDR4, there is no required termination on the PCB of the address/control bus of an LPDDR4
 configuration. All termination is handled internally (on-die). Thus, VTT does not apply for LPDDR4. configuration. All termination is handled internally (on-die). Thus, VTT does not apply for LPDDR4.
  
  
-==== Routing ====+===== Routing =====
 ^                ^ TI     ^ RockChip ref design ^ ^                ^ TI     ^ RockChip ref design ^
 | SE impedance   | 40 Ohm | 4mil\0.035u\0.082 prepreg Dk4.5 - ??? Ohm | | SE impedance   | 40 Ohm | 4mil\0.035u\0.082 prepreg Dk4.5 - ??? Ohm |
Строка 179: Строка 201:
  
  
-==== Docs ====+===== Docs =====
 ^ Application Notes ^^^^^^^ ^ Application Notes ^^^^^^^
 ^ link ^ ext ^ description ^ manufacturer ^ version ^ date ^ lang ^ ^ link ^ ext ^ description ^ manufacturer ^ version ^ date ^ lang ^
wiki/cmp/mem/lpddr4/start.1701096421.txt.gz · Последнее изменение: 2023/11/27 14:47 — Roman Abakumov

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