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| wiki:cmp:mem:lpddr4:start [2022/10/26 14:59] – Roman Abakumov | wiki:cmp:mem:lpddr4:start [2025/09/26 10:43] (текущий) – Roman Abakumov | ||
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| Строка 1: | Строка 1: | ||
| - | ===== LPDDR4 (LPDDR4x) ===== | + | ====== LPDDR4(4x) ====== |
| - | ==== Manufacturers ==== | + | ===== Manufacturers |
| | https:// | | https:// | ||
| | https:// | | https:// | ||
| Строка 15: | Строка 15: | ||
| ^ ^^^ | ^ ^^^ | ||
| | https:// | | https:// | ||
| + | | https:// | ||
| - | {{ : | + | {{ : |
| - | ==== low power ==== | + | ==== Table ==== |
| + | | MT53D512M32D2DS-053WT: | ||
| + | | H2AB32G32D6CPAAI | ||
| + | | W66BQ6NB | ||
| + | | W66CQ2NQ | ||
| + | | NCLD4C1MA256M32 | ||
| + | | NCLD4C2MA512M32 | ||
| + | | NCLD4C2MA768M32 | ||
| + | | NCLD4C2MA001G32 | ||
| + | |||
| + | |||
| + | ===== Configurations ===== | ||
| + | ^ Capacity ^ Width ^ CS (Rank) ^ Channels ^ Dies ^ Link ^ Diagram ^ | ||
| + | | 16 Gb | x16 | 1 CS | 1 Channel | 1 Die | [[https:// | ||
| + | | 16 Gb | x16+x16 | 1 CS | 2 Channel | 1 Die | [[https:// | ||
| + | | 8 Gb | x16+x16 | 1 CS | 2 Channel | 1 Die | [[https:// | ||
| + | | 16 Gb | x16+x16 | 1 CS | 2 Channel | 1 Die | [[https:// | ||
| + | | 16 Gb | x16+x16 | 1 CS | 2 Channel | 1 Die | [[https:// | ||
| + | | 16 Gb | x16+x16 | 1 CS | 2 Channel | 2 Die | [[https:// | ||
| + | | 32 Gb | x16+x16 | 1 CS | 2 Channel | 2 Die | [[https:// | ||
| + | | 32 Gb | x16+x16 | 1 CS | 2 Channel | 2 Die | [[https:// | ||
| + | | 16 Gb | x16+x16 | 2 CS | 2 Channel | 2 Die | [[https:// | ||
| + | | 32 Gb | x16+x16 | 2 CS | 2 Channel | 2 Die | [[https:// | ||
| + | | 32 Gb | x16+x16 | 2 CS | 2 Channel | 4 Die | [[https:// | ||
| + | | 64 Gb | X16+x16 | 2 CS | 2 Channel | 4 Die | [[https:// | ||
| + | | 64 Gb | x16+x16 | 2 CS | 2 Channel | 4 Die | [[https:// | ||
| + | | 64 Gb | x16+x16 | 2 CS | 2 Channel | 4 Die | [[https:// | ||
| + | | 128 Gb | x16+x16 | 2 CS | 2 Channel | 8 Die | [[https:// | ||
| + | |||
| + | |||
| + | |||
| + | ===== SKHynix ===== | ||
| + | {{tablelayout? | ||
| + | | H9HCNNNCPUMLXR-NEE | ||
| + | | H9HCNNNBKUMLXR-NEE | ||
| + | | H9HCNNNBPUMLHR-NME | ||
| + | | H9HCNNNBPUMLHR-NLE | ||
| + | | H9HCNNN8KUMLHR-NME | ||
| + | | H9HCNNN8KUMLHR-NLE | ||
| + | | H9HCNNNCPUMLXR-NEE | ||
| + | | H9HCNNNCPUMLXR-NEI | ||
| + | | H9HCNNNCPUMLHR-NME | ||
| + | | H9HCNNNBKUMLXR-NEI | ||
| + | | H9HCNNNBKUMLXR-NEE | ||
| + | | H9HCNNNBKUMLHR-NME | ||
| + | | H9HCNNNBKUMLHR-NMI | ||
| + | | H9HCNNNBPUMLHR-NME | ||
| + | | H9HCNNNBPUMLHR-NMI | ||
| + | | H9HCNNNBPUMLHR-NLE | ||
| + | | H54G36AYRBX257 | ||
| + | | H54G36AYRJX246 | ||
| + | | H54G38AYRBX259 | ||
| + | | H9HCNNN8KUMLHR-NME | ||
| + | | H9HCNNN8KUMLHR-NMI | ||
| + | | H54G26AYRBX256 | ||
| + | | H9HCNNN4KUMLHR-NMI | ||
| + | | H9HCNNN4KUMLHR-NME | ||
| + | | H54G56BYYQX046 | ||
| + | | H54G56BYYVX046 | ||
| + | | H54G56BYYPX046 | ||
| + | | H9HCNNNCPUMLHR-NMN | ||
| + | | H9HCNNNCPUMLHR-NMO | ||
| + | | H54G46BYYVX053 | ||
| + | | H54G46BYYPX053 | ||
| + | | H54G46BYYQX053 | ||
| + | | H9HCNNNBPUMLHR-NMO | ||
| + | | H9HCNNNBPUMLHR-NMN | ||
| + | | H9HCNNNBKUMLHR-NMO | ||
| + | | H9HCNNNBKUMLHR-NMN | ||
| + | | H9HCNNN8KUMLHR-NMN | ||
| + | | H9HCNNN8KUMLHR-NMO | ||
| + | | H9HCNNN4KUMLHR-NMO | ||
| + | | H9HCNNN4KUMLHR-NMP | ||
| + | | H9HCNNN4KUMLHR-NMN | ||
| + | |||
| + | |||
| + | {{tablelayout? | ||
| + | | H9HCNNNFAMMLXR-NEE | ||
| + | | H9HCNNNFAMALTR-NME | ||
| + | | H9HCNNNCPMMLXR-NEE | ||
| + | | H9HCNNNCPMALHR-NEE | ||
| + | | H9HCNNNBKMALHR-NEE | ||
| + | | H9HCNNNBKMMLXR-NEE | ||
| + | | H54G66BYYJX104 | ||
| + | | H9HCNNNFAMMLXR-NEI | ||
| + | | H9HCNNNFAMMLXR-NEE | ||
| + | | H9HCNNNCPMMLXR-NEE | ||
| + | | H54G56BYYJX089 | ||
| + | | H9HCNNNCPMMLXR-NEI | ||
| + | | H9HCNNNCPMMLHR-NMI | ||
| + | | H9HCNNNCPMMLHR-NME | ||
| + | | H54G46BYYJX085 | ||
| + | | H9HCNNNBKMMLXR-NEI | ||
| + | | H9HCNNNBKMMLXR-NEE | ||
| + | | H9HCNNNBKMMLHR-NME | ||
| + | | H9HCNNNBKMMLHR-NMI | ||
| + | | H9HCNNN4KMMLHR-NME | ||
| + | | H54G66BYYVX104 | ||
| + | | H54G66BYYPX104 | ||
| + | | H54G66BYYQX104 | ||
| + | | H54G56BYYPX089 | ||
| + | | H54G56BYYVX089 | ||
| + | | H9HCNNNCPMMLHR-NMO | ||
| + | | H9HCNNNCPMMLHR-NMN | ||
| + | | H54G46BYYQX085 | ||
| + | | H54G46BYYVX085 | ||
| + | | H54G46BYYPX085 | ||
| + | | H9HCNNNBKMMLHR-NMO | ||
| + | | H9HCNNNBKMMLHR-NMN | ||
| + | | H54G38AYRPX264 | ||
| + | | H54G36AYRPX246 | ||
| + | | H54G36AYRQX246 | ||
| + | | H54G38AYRVX264 | ||
| + | | H54G36AYRVX246 | ||
| + | | H54G38AYRQX264 | ||
| + | | H54G26AYRPX066 | ||
| + | | H54G26AYRVX066 | ||
| + | | H54G26AYRQX066 | ||
| + | | H9HCNNN4KMMLHR-NMP | ||
| + | | H9HCNNN4KMMLHR-NMO | ||
| + | | H9HCNNN4KMMLHR-NMN | ||
| + | |||
| + | |||
| + | ===== low power ===== | ||
| LPDDR4X is a variant of LPDDR4, with the difference of additional power savings by reducing the I/O voltage from 1.1 V to 0.6 V. | LPDDR4X is a variant of LPDDR4, with the difference of additional power savings by reducing the I/O voltage from 1.1 V to 0.6 V. | ||
| - | ==== ECC ==== | + | ===== ECC ===== |
| ECC is supported on the LPDDR4 interface. Unlike traditional ECC interfaces which require dedicated memory | ECC is supported on the LPDDR4 interface. Unlike traditional ECC interfaces which require dedicated memory | ||
| pins and devices, ECC is supported inline. The ECC system impact is in interface bandwidth and overall memory | pins and devices, ECC is supported inline. The ECC system impact is in interface bandwidth and overall memory | ||
| Строка 33: | Строка 157: | ||
| * есть p\n с ECC (https:// | * есть p\n с ECC (https:// | ||
| - | ==== Termination ==== | + | ===== Termination |
| LPDDR4 memories have software configurable on-die termination for both the data group nets. The DDR | LPDDR4 memories have software configurable on-die termination for both the data group nets. The DDR | ||
| subsystem also contains software configurable on-die termination for the address/ | subsystem also contains software configurable on-die termination for the address/ | ||
| Строка 39: | Строка 163: | ||
| - | ==== VREF ==== | + | ===== VREF ===== |
| LPDDR4 memories generate their own VREFCA and VREFDQ internally for the address / command bus and data bus, | LPDDR4 memories generate their own VREFCA and VREFDQ internally for the address / command bus and data bus, | ||
| respectively. Similarly, the DDR PHY also provides its own reference voltage for the data group nets | respectively. Similarly, the DDR PHY also provides its own reference voltage for the data group nets | ||
| Строка 46: | Строка 170: | ||
| - | ==== VTT ==== | + | ===== VTT ===== |
| Unlike DDR3 and DDR4, there is no required termination on the PCB of the address/ | Unlike DDR3 and DDR4, there is no required termination on the PCB of the address/ | ||
| configuration. All termination is handled internally (on-die). Thus, VTT does not apply for LPDDR4. | configuration. All termination is handled internally (on-die). Thus, VTT does not apply for LPDDR4. | ||
| - | ==== Routing ==== | + | ===== Routing |
| ^ ^ TI ^ RockChip ref design ^ | ^ ^ TI ^ RockChip ref design ^ | ||
| | SE impedance | | SE impedance | ||
| Строка 77: | Строка 201: | ||
| - | ==== Docs ==== | + | ===== Docs ===== |
| ^ Application Notes ^^^^^^^ | ^ Application Notes ^^^^^^^ | ||
| ^ link ^ ext ^ description ^ manufacturer ^ version ^ date ^ lang ^ | ^ link ^ ext ^ description ^ manufacturer ^ version ^ date ^ lang ^ | ||
wiki/cmp/mem/lpddr4/start.1666796340.txt.gz · Последнее изменение: 2022/10/26 14:59 — Roman Abakumov
Если не указано иное, содержимое этой вики предоставляется на условиях следующей лицензии: CC Attribution-Share Alike 4.0 International
